D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 166

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
6.4.3
Table 6.4 shows the data buses used, and the valid strobes, for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 6.4
Area
8-bit
access
area
16-bit
access
area
Notes: 1. Undetermined data means that unpredictable data is output.
6.4.4
The initial state of each area is basic bus interface, three-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the following sections should be referred to for further details: 6.4, Basic Bus Interface,
6.5, DRAM Interface, 6.8, Burst ROM Interface.
Area 0: When area 0 external space is accessed, the CS
Either basic bus interface or burst ROM interface can be selected for area 0.
The size of area 0 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Areas 1 and 6: When area 1 and 6 external space is accessed, the CS
respectively can be output.
Only the basic bus interface can be used for areas 1 and 6.
Rev.5.00 Sep. 12, 2007 Page 136 of 764
REJ09B0396-0500
2. Invalid means that the bus is in the input state and the input is ignored.
Memory Areas
Valid Strobes
Access
Size
Byte
Byte
Word
Data Buses Used and Valid Strobes
Read/Write
Read
Write
Read
Write
Read
Write
Address Valid Strobe
⎯
⎯
Even
Odd
Even
Odd
⎯
⎯
RD
HWR
RD
HWR
LWR
RD
HWR, LWR
0
signal can be output.
Upper Data Bus
(D
Valid
Valid
Invalid
Valid
Undetermined
data
Valid
Valid
15
to D
1
and CS
8
)
6
pin signals
Lower Data Bus
(D
Invalid
Undetermined
data
Invalid
Valid
Undetermined
data
Valid
Valid
Valid
7
to D
0
)