D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 193

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM.
The H8/3006 and H8/3007 have a function that places the DRAM in self-refresh mode when the
chip enters software standby mode.
To use the self-refresh function, set the SRFMD bit to 1 in DRCRA. When a SLEEP instruction is
subsequently executed in order to enter software standby mode, the CAS and RAS signals are
output and the DRAM enters self-refresh mode, as shown in figure 6.28.
When the chip exits software standby mode, CAS and RAS outputs go high.
The following conditions must be observed when the self-refresh function is used:
• When burst access is selected, RAS up mode must be selected before executing a SLEEP
• The instruction immediately following a SLEEP instruction must not be located in an area
The self-refresh function will not work properly unless the above conditions are observed.
instruction in order to enter software standby mode. Therefore, if RAS down mode has been
selected, the RDM bit in DRCRA must be cleared to 0 and RAS up mode selected before
executing the SLEEP instruction. Select RAS down mode again after exiting software standby
mode.
designated as DRAM space.
Address bus
PB4(UCAS)
PB5(LCAS)
CS
RFSH
RD(WE)
n
(RAS)
φ
Figure 6.28 Self-Refresh Timing (CSEL = 0)
Software standby
High-impedance
mode
Rev.5.00 Sep. 12, 2007 Page 163 of 764
Oscillation stabilization
time
REJ09B0396-0500
6. Bus Controller