D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 428

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11. Programmable Timing Pattern Controller (TPC)
Address H'FFFA6
Bit
Initial value
Read/Write
11.2.7
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP
Bit
Initial value
Read/Write
If a bit is enabled for TPC output by NDERA, then when the 16-bit timer compare match event
selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically
transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled,
the bit value is not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0⎯Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP
Rev.5.00 Sep. 12, 2007 Page 398 of 764
REJ09B0396-0500
Bits 7 to 0
NDER7 to NDER0
0
1
7
to TP
Next Data Enable Register A (NDERA)
0
) on a bit-by-bit basis.
NDER7
R/W
⎯
⎯
7
1
7
0
Description
TPC outputs TP
(NDR7 to NDR0 are not transferred to PA
TPC outputs TP
(NDR7 to NDR0 are transferred to PA
NDER6
7
Reserved bits
to TP
R/W
⎯
⎯
6
1
6
0
0
) on a bit-by-bit basis.
NDER5
R/W
⎯
⎯
5
1
5
0
7
7
to TP
to TP
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
NDER4
R/W
0
0
⎯
⎯
are disabled
are enabled
4
1
4
0
NDER3
NDR11
R/W
R/W
3
0
3
0
7
to PA
Next data 11 to 8
These bits store the next output
data for TPC output group 2
NDER2
NDR10
7
R/W
R/W
to PA
2
0
2
0
0
)
0
)
NDER1
NDR9
R/W
R/W
1
0
1
0
NDER0
(Initial value)
NDR8
R/W
R/W
0
0
0
0