D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 106

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4. Exception Handling
4.4
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
4.5
Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
Rev.5.00 Sep. 12, 2007 Page 76 of 764
REJ09B0396-0500
SP−4
SP−3
SP−2
SP−1
SP (ER7) →
Legend:
PC
PC
PC
CCR:
SP:
Notes: 1. PC indicates the address of the first instruction that will be executed after return.
E
H
L
:
:
:
Bits 23 to 16 of program counter (PC)
Bits 15 to 8 of program counter (PC)
Bits 7 to 0 of program counter (PC)
Condition code register
Stack pointer
2. Registers must be saved in word or longword size at even addresses.
Trap Instruction
Stack Status after Exception Handling
Before exception handling
Figure 4.5 Stack after Completion of Exception Handling
Stack area
Pushed on stack
SP (ER7)
SP+1
SP+2
SP+3
SP+4
→
After exception handling
CCR
PC
PC
PC
E
H
L
Even address