D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 514

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13. Serial Communication Interface
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of DMAC:
• When an external clock source is used for the serial clock, after the DMAC updates TDR,
• To have the DMAC read RDR, be sure to select the corresponding SCI receive-data-full
Rev.5.00 Sep. 12, 2007 Page 484 of 764
REJ09B0396-0500
allow an inversion of at least five system clock (φ) cycles before input of the serial clock to
start transmitting. If the serial clock is input within four states of the TDR update, a
malfunction may occur. (See figure 13.22)
interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.
D = 0.5, F = 0
M =
M =
M:
N:
D:
L:
F:
= 46.875%
(0.5 −
Receive margin (%)
Ratio of clock frequency to bit rate (N = 16)
Clock duty cycle (L = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
(0.5 −
2 × 16
1
2N
1
) − (L − 0.5) F −
) × 100%
D − 0.5
N
(1 + F)
. . . . . . . . (1)
. . . . . . . . (2)
× 100%