D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 102

MCU 3V 0K 100-TQFP

D13007VX13V

Manufacturer Part Number
D13007VX13V
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of D13007VX13V

Core Processor
H8/300H
Core Size
16-Bit
Speed
13MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
4. Exception Handling
4.2
4.2.1
A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the
chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the
on-chip supporting modules. Reset exception handling begins when the RES pin changes from
low to high.
The chip can also be reset by overflow of the watchdog timer. For details see section 12,
Watchdog Timer.
4.2.2
The chip enters the reset state when the RES pin goes low.
To ensure that the chip is properly reset, hold the RES pin low for at last 20 ms at power-up. To
reset the chip during operation, hold the RES pin low for at least 10 system clock (φ) cycles. See
appendix D.2, Pin States at Reset, for the states of the pins in the reset state.
When the RES pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows.
• The internal state of the CPU and the registers of the on-chip supporting modules are
• The contents of the reset vector address (H'0000 to H'0003) are read, and program execution
Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in
modes 2 and 4.
Rev.5.00 Sep. 12, 2007 Page 72 of 764
REJ09B0396-0500
initialized, and the I bit is set to 1 in CCR.
starts from the address indicated in the vector address.
Reset
Overview
Reset Sequence

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