D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 499

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

In transmitting serial data, the SCI operates as follows:
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
Figure 13.11 shows an example of SCI transmit operation using a multiprocessor format.
TDRE
TEND
recognizes that TDR contains new data, and loads this data from TDR into TSR.
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
⎯ Start bit: One 0 bit is output.
⎯ Transmit data: 7 or 8 bits are output, LSB first.
⎯ Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
⎯ Stop bit(s): One or two 1 bits (stop bits) are output.
⎯ Mark state: Output of 1 bits continues until the start bit of the next transmit data.
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit,
then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-
end interrupt (TEI) is requested at this time
1
TXI interrupt
request
Start
bit
0
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
D0
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
Figure 13.11 Example of SCI Transmit Operation
D1
1 frame
Data
D7
processor
Multi-
TXI interrupt
request
bit
0/1
Stop
bit
1
Start
bit
0
Rev.5.00 Sep. 12, 2007 Page 469 of 764
D0
13. Serial Communication Interface
D1
Data
D7
processor
Multi-
bit
0/1
REJ09B0396-0500
request
Stop
bit
TEI interrupt
1
state
Idle (mark)