D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 288

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8. I/O Ports
When bits in P8DDR bit are set to 1, P8
P8DDR are cleared to 0, the corresponding pins become input ports. Following a reset P8
functions as the CS
When the refresh enable bit (RFSHE) in DRCRA is set to 1, P8
RFSHE is cleared to 0, P8
details see table 8.8.
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode
P8DDR retains its previous setting. Therefore, when port 8 functions as an input/output port, if a
transition is made to software standby mode while a P8DDR bit is set to 1, the corresponding pin
maintains its output state.
Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data
for port 8. When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR
bit is returned. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin level is
read.
Bits 7 to 5 are reserved. They cannot be modified and always are read as 1.
Bit
Initial value
Read/Write
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev.5.00 Sep. 12, 2007 Page 258 of 764
REJ09B0396-0500
⎯
⎯
7
1
0
output, while the other three pins are input ports.
Reserved bits
0
becomes an input/output port according to the P8DDR setting. For
⎯
⎯
6
1
⎯
⎯
5
1
4
to P8
1
become CS
R/W
P8
4
0
4
R/W
P8
0
3
0
Port 8 data 4 to 0
These bits store data
for port 8 pins
to CS
3
0
is used for RFSH output. When
3
output pins. When bits in
R/W
P8
2
0
2
R/W
P8
1
0
1
R/W
P8
0
0
4
0