D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 153

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than
000 must not be performed.
Bit 4⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 3⎯Burst Access Enable (BE): Enables or disables burst access to DRAM space. DRAM
space burst access is performed in fast page mode.
Bit 3
BE
0
1
Bit 2⎯RAS Down Mode (RDM): Selects whether to wait for the next DRAM access with the
RAS signal held low (RAS down mode), or to drive the RAS signal high again (RAS up mode),
when burst access is enabled for DRAM space (BE = 1), and access to DRAM is interrupted.
Caution is required when the HWR and LWR are used as the UCAS and LCAS output pins. For
details, see RAS Down Mode and RAS Up Mode in section 6.5.10, Burst Operation.
Bit 2
RDM
0
1
Bit 1⎯Self-Refresh Mode (SRFMD): Specifies DRAM self-refreshing in software standby
mode.
When any of areas 2 to 5 is designated as DRAM space, DRAM self-refreshing is possible when a
transition is made to software standby mode after the SRFMD bit has been set to 1.
The normal access state is restored when software standby mode is exited, regardless of the
SRFMD setting.
Bit 1
SRFMD
0
1
Description
Burst disabled (always full access)
DRAM space access performed in fast page mode
Description
DRAM interface: RAS up mode selected
DRAM interface: RAS down mode selected
Description
DRAM self-refreshing disabled in software standby mode
DRAM self-refreshing enabled in software standby mode
Rev.5.00 Sep. 12, 2007 Page 123 of 764
REJ09B0396-0500
6. Bus Controller
(Initial value)
(Initial value)
(Initial value)