D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 552

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

15. A/D Converter
15.3
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 15.2 shows the data flow for access to an A/D data register.
Rev.5.00 Sep. 12, 2007 Page 522 of 764
REJ09B0396-0500
CPU Interface
Figure 15.2 A/D Data Register Access Operation (Reading H'AA40)
Upper-byte read
Lower-byte read
CPU
(H'AA)
CPU
(H'40)
Note: n = A to D
Bus interface
Bus interface
ADDRnH
ADDRnH
(H'AA)
(H'AA)
ADDRnL
ADDRnL
(H'40)
(H'40)
TEMP
TEMP
(H'40)
(H'40)
Module data bus
Module data bus