D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 778

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Appendix D Pin States
Port Name
Pin Name
PB
PB
Legend:
H:
L:
T:
Keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR:
Notes: 1. Low only when WDT overflow causes a reset.
Rev.5.00 Sep. 12, 2007 Page 748 of 764
REJ09B0396-0500
5
7
, PB
, PB
4
6
High
Low
High-impedance state
Data direction register
2. When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all
3. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
4. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
5. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
6. When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
7 When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
8. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to 1.
9. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is cleared
10. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
11. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
12. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
cleared to 0.
set to 1.
register A) is 010, 100, or 101.
register A) is other than 010, 100, or 101.
cleared to 0.
set to 1.
to 0.
register A) is 101.
register A) is other than 101, and bit CS5E in CSCR (chip select control register) is set
to 1.
register A) is other than 101, and bit CS5E in CSCR (chip select control register) is
cleared to 0.
Mode
1 to 4
1 to 4
Reset
T
T
Hardware
Standby
Mode
T
T
Software Standby Mode
• CAS output*
• Otherwise*
Keep
[SSOE = 0]
T
[SSOE = 1]
H
Keep
17
16
Bus-Released State
• CAS output*
• Otherwise*
Keep
T
Keep
17
16
I/O port
Program
Execution
State
• CAS output
• Otherwise
UCAS,
LCAS
I/O port