D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 264

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7. DMA Controller
7.4.10
During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or
by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer
of the current byte or word. If there is a transfer request at this point, the DMAC requests the bus
right again. Figure 7.20 shows an example of the timing of insertion of a refresh cycle during a
burst transfer on channel 0.
Rev.5.00 Sep. 12, 2007 Page 234 of 764
REJ09B0396-0500
φ
Address
bus
RD
HWR
LWR
φ
Address
bus
RD
HWR
,
External Bus Requests, DRAM Interface, and DMAC
DMAC cycle
(channel 1)
T
1
T
Figure 7.20 Bus Timing of DRAM Interface and DMAC
1
Figure 7.19 Timing of Multiple-Channel Operations
T
2
DMAC cycle (channel 0)
T
2
T
1
T
1
T
CPU
cycle
2
T
2
T
1
T
d
T
2
T
1
DMAC cycle
(channel 0A)
T
1
T
2
T
2
T
T
1
Refresh
cycle
1
T
T
2
2
T
T
1
d
CPU
cycle
T
T
2
DMAC cycle (channel 0)
1
T
T
d
2
T
T
1
1
DMAC cycle
(channel 1)
T
T
2
2
T
T
1
1
T
T
2
2