D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 210

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall
(assertion) of CSn may occur simultaneously. An example of the operation is shown in figure
6.45.
If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in
BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0
bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following
bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal,
it is possible that the low-level output of RD in the preceding read cycle and the low-level output
of CSn in the following bus cycle will overlap.
Rev.5.00 Sep. 12, 2007 Page 180 of 764
REJ09B0396-0500
(UCAS/LCAS)
Address bus
HWR/LWR
Figure 6.43 Example of Idle Cycle Operation (3) (HWR/LWR Used as UCAS/LCAS)
Figure 6.44 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles)
CSn
φ
(a) Idle cycle not inserted
(DRAM access cycle)
T
p
Bus cycle A
UCAS/LCAS
Address bus
Address bus
T
r
T
c1
Simultaneous change of
HWR/LWR and CSn
RD
T
φ
c2
Bus cycle B
T
1
T
External read
1
T
2
T
2
(UCAS/LCAS)
T
Address bus
3
HWR/LWR
T
DRAM space read
p
CSn
T
φ
r
(DRAM access cycle) Bus cycle B
T
T
c1
Bus cycle A
p
(b) Idle cycle inserted
T
T
r
c2
T
c1
T
c2
T
i
T
1
T
2