D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 178

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
6.5.3
When DRAM space is accessed, the row address and column address are multiplexed. The address
multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number
of bits in the DRAM column address. Table 6.6 shows the correspondence between the settings of
MXC1 and MXC0 and the address multiplexing method.
Table 6.6
Column
address
Note:
6.5.4
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, × 16-bit organization DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D
space both the upper and lower halves of the data bus, D
Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data
Size and Data Alignment.
Rev.5.00 Sep. 12, 2007 Page 148 of 764
REJ09B0396-0500
Row
address
* Row address bit A
DRCRB
MXC1 MXC0 Bits
1
⎯
Address Multiplexing
0
Data Bus
Settings of Bits MXC1 and MXC0 and Address Multiplexing Method
0
1
0
1
⎯
Column
Address
10 bits
Illegal
setting
⎯
8 bits
9 bits
20
is not multiplexed in 1-Mbyte mode.
A
A
⎯
A
A
A
23
23
23
23
23
to A
to A
to A
to A
to A
13
13
13
13
13
A
A
⎯
A
A
A
12
20
12
12
12
* A
A
A
⎯
A
A
11
11
11
19
20
* A
A
A
A
⎯
A
10
20
10
18
19
15
* A
to D
15
A
⎯
A
A
A
to D
9
17
18
19
9
8
Address Pins
, is enabled, while in 16-bit DRAM
A
A
⎯
A
A
A
0
8
18
8
16
17
, are enabled.
A
A
A
A
⎯
A
7
17
7
15
16
A
A
⎯
A
A
A
6
14
15
16
6
A
A
⎯
A
A
A
5
15
5
13
14
A
A
A
A
⎯
A
4
14
4
12
13
A
A
⎯
A
A
A
3
11
12
13
3
A
A
⎯
A
A
A
2
12
2
10
11
A
A
A
A
⎯
A
1
11
1
9
10
A
A
⎯
A
A
A
0
8
9
10
0