D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 208

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
6.9
6.9.1
When the H8/3006 and H8/3007 chip accesses external space, it can insert a 1-state idle cycle (T
between bus cycles in the following cases: (1) when read accesses between different areas occur
consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when external
address space other than DRAM space is accessed immediately after a DRAM space access. By
inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, which
has a long output floating time, and high-speed memory, I/O interfaces, and so on.
The ICIS1 and ICIS0 bits in BCR both have an initial value of 1, so that an idle cycle is inserted in
the initial state. If there are no data collisions, the ICIS bits can be cleared.
Consecutive Reads between Different Areas: If consecutive reads between different areas occur
while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.41 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.42 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Rev.5.00 Sep. 12, 2007 Page 178 of 764
REJ09B0396-0500
Address bus
Data bus
Idle Cycle
Operation
RD
φ
(a) Idle cycle not inserted
Figure 6.41 Example of Idle Cycle Operation (1) (ICIS1 = 1)
Bus cycle A Bus cycle B
T
1
Long buffer-off time
T
2
T
3
T
1
T
2
Data collision
Address bus
Data bus
RD
φ
Bus cycle A Bus cycle B
T
(b) Idle cycle inserted
1
T
2
T
3
T
i
T
1
T
2
I
)