D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 283

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

P6
PSTOP bit in MSTCRH is cleared to 0 (initial value), and an input port if this bit is set to 1.
When P6
corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.
P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode,
it retains its previous setting. When port 6 functions as a generic input/output port, if a P6DDR bit
is set to 1, the corresponding pin maintains its output state in software standby mode.
Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data
for port 6. When port 6 functions as an output port, the value of this register is output.
Bit
Initial value
Read/Write
Note: * Determined by pin P6
Bit 7 returns 1 if read when the PSTOP bit in MSTCRH is 0, and returns the logic level of pin P6
if read when the PSTOP bit is 1. This bit cannot be modified.
Bits 6 to 3 are reserved; they can be read and written to, but cannot be used as ports.
The P6DR value is returned if P6DR is read while the corresponding bit (P6
P6DDR is set to 1, and an undefined value is returned if P6DR is read while the corresponding bit
is cleared to 0.
For bits 2 to 0, the pin logic level is returned if the bit is read while the corresponding bit in
P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the corresponding
bit in P6DDR is set to 1.
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
7
functions as the clock output pin (φ) or an input port. P6
2
to P6
0
function as input/output ports, the pin becomes an output port if the
P6
R
7
*
7
R/W
P6
6
0
7
6
.
Reserved bit
R/W
P6
5
0
5
Data 7, 2 to 0 for port 6 pins
Bits storing data for port 6 pins
R/W
P6
4
0
4
Rev.5.00 Sep. 12, 2007 Page 253 of 764
R/W
P6
3
0
7
3
is the clock input pin (φ) if the
R/W
P6
2
0
2
6
DDR to P6
R/W
P6
1
0
REJ09B0396-0500
1
8. I/O Ports
R/W
P6
3
DDR) in
0
0
0
7