D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 191

MCU 3V 0K 100-TQFP

D13007VX13V

Manufacturer Part Number
D13007VX13V
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of D13007VX13V

Core Processor
H8/300H
Core Size
16-Bit
Speed
13MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (T
and two RAS output cycle (T
precharge cycle. When the TPC bit is set to 1 in DRCRB, RAS signal output is delayed by one
cycle. This does not affect the timing of UCAS and LCAS output.
Refresh request signal
and CMF bit setting signal
RTCNT
RTCOR
φ
Figure 6.26 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0)
(UCAS/LCAS)
Address bus
PB4/PB5
CS
RD(WE)
RFSH
n
(RAS)
AS
φ
R1
Figure 6.25 Compare Match Timing
, T
R2
) states. Either one or two states can be selected for the RAS
T
Rp
N
High
High
Area 2 start address
T
R1
Rev.5.00 Sep. 12, 2007 Page 161 of 764
N
T
R2
H'00
REJ09B0396-0500
6. Bus Controller
RP
) state,

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