DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 892
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 892 of 1246
- Download datasheet (7Mb)
• The division ratio can be changed while the chip is operating. The clock output from the φ pin
• Do not set the DIV bit and bits SCK2 to SCK0 simultaneously. First set the DIV bit, then bits
Bit 5
DIV
0
1
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): When the DIV bit is cleared to 0,
these bits select the bus master clock; when the DIV bit is set to 1, they select the division ratio of
the clock supplied to the entire chip.
Bit 2
SCK2
0
1
Rev.4.00 Sep. 07, 2007 Page 860 of 1210
REJ09B0245-0400
will also change when the division ratio is changed. The frequency of the clock output from
the φ pin in this case will be as follows:
Where: EXTAL: Crystal resonator or external clock frequency
SCK2 to SCK0.
Bit 1
SCK1
0
1
0
1
Description
When bits SCK2 to SCK0 are set to other than high-speed mode, medium-speed
mode is set
When bits SCK2 to SCK0 are set to other than high-speed mode, a divided clock is
supplied to the entire chip
φ = EXTAL × n
n:
Bit 0
SCK0
0
1
0
1
0
1
—
Division ratio (n = φ/2, φ/4, or φ/8)
Bus master is in high-speed
mode
Medium-speed clock is φ/2
Medium-speed clock is φ/4
Medium-speed clock is φ/8
Medium-speed clock is φ/16
Medium-speed clock is φ/32
—
DIV = 0
(Initial value)
Description
DIV = 1
Bus master is in high-speed
mode
Clock supplied to entire chip is φ/2
Clock supplied to entire chip is φ/4
Clock supplied to entire chip is φ/8
—
—
—
(Initial value)
(Initial value)
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