DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 575
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 575 of 1246
- Download datasheet (7Mb)
11.3
11.3.1
PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set
to 1. In this state the corresponding PODR contents are output.
When the compare match event specified by PCR occurs, the corresponding NDR bit contents are
transferred to PODR to update the output values.
Figure 11.2 illustrates the PPG output operation and table 11.3 summarizes the PPG operating
conditions.
Table 11.3 PPG Operating Conditions
NDER
0
1
Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the
next compare match. For details of non-overlapping operation, see section 11.3.4, Non-
Overlapping Pulse Output.
Pulse output pin
Operation
Overview
1
1
DDR
0
0
Generic output port
compare match occurs, the NDR bit value is transferred to the PODR bit)
PPG pulse output
Pin Function
Generic input port
Generic input port (but the PODR bit is a read-only bit, and when
DDR
Q
Figure 11.2 PPG Output Operation
Normal output/inverted output
Q
NDER
Q
PODR
C
Output trigger signal
Rev.4.00 Sep. 07, 2007 Page 543 of 1210
D
Q
NDR
D
REJ09B0245-0400
Internal data bus
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