DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 591
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 591 of 1246
- Download datasheet (7Mb)
The timer output can be freely controlled by these compare match signals and the settings of bits
OS1 and OS0 in TCSR.
TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode.
12.2.3
TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a
single 16-bit register so they can be accessed together by a word transfer instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFB flag in TCSR is set. Note, however, that comparison is disabled during the
T
The timer output can be freely controlled by these compare match signals and the settings of
output select bits OS3 and OS2 in TCSR.
TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode.
12.2.4
TCR0 and TCR1 are 8-bit readable/writable registers that select the clock source and the time at
which TCNT is cleared, and enable interrupts.
TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode.
For details of this timing, see section 12.3, Operation.
2
Bit
Initial value :
R/W
Bit
Initial value :
R/W
state of a TCOR write cycle.
Time Constant Registers B0 and B1 (TCORB0, TCORB1)
Time Control Registers 0 and 1 (TCR0, TCR1)
:
:
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
:
15
CMIEB
1
R/W
7
0
14
1
13
CMIEA
1
R/W
6
0
TCORB0
12
1
11
1
OVIE
R/W
5
0
10
1
CCLR1
9
1
R/W
0
4
8
1
Rev.4.00 Sep. 07, 2007 Page 559 of 1210
CCLR0
7
1
R/W
3
0
6
1
5
1
CKS2
R/W
2
0
TCORB1
4
1
REJ09B0245-0400
3
1
CKS1
R/W
1
0
2
1
1
1
CKS0
R/W
0
0
0
1
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