DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 690

IC H8S/2300 MCU FLASH 144QFP

DF2339VFC25V

Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2339VFC25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Thus the receive margin in asynchronous mode is given by formula (1) below.
Where M : Receive margin (%)
Assuming values of F = 0 and D = 0.5 in formula (1), a receive margin of 46.875% is given by
formula (2) below.
When D = 0.5 and F = 0,
However, this is a theoretical value, and a margin of 20% to 30% should be allowed in system
design.
Rev.4.00 Sep. 07, 2007 Page 658 of 1210
REJ09B0245-0400
Internal base
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = | (0.5 –
M = (0.5 –
N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
= 46.875%
Figure 14.21 Receive Data Sampling Timing in Asynchronous Mode
0
2 × 16
2N
8 clocks
Start bit
1
1
) – (L – 0.5) F –
) × 100%
16 clocks
7
| D – 0.5 |
N
15 0
(1 + F) | × 100%
D0
7
... Formula (1)
... Formula (2)
15 0
D1

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