DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 132
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 132 of 1246
- Download datasheet (7Mb)
5.2
5.2.1
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI.
Only bits 5 to 3, and 1 are described here; for details of the other bits, see section 3, MCU
Operating Modes.
SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two
interrupt control modes for the interrupt controller.
Bit 5
INTM1
0
1
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG
0
1
Bit 1—IRQ Input Pin Select (IRQPAS): Selects switching of the pins that can be used for input
of IRQ4 to IRQ7. IRQ4 to IRQ7 input is always performed from one of the ports.
Rev.4.00 Sep. 07, 2007 Page 100 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Register Descriptions
System Control Register (SYSCR)
Bit 4
INTM0
1
1
0
0
Description
Interrupt request generated at falling edge of NMI input
Interrupt request generated at rising edge of NMI input
:
:
R/W
—
Interrupt
Control Mode
0
—
2
—
7
0
—
—
6
0
Description
Interrupts are controlled by I bit
Setting prohibited
Interrupts are controlled by bits I2 to I0, and IPR
Setting prohibited
INTM1
R/W
5
0
INTM0
R/W
4
0
NMIEG
R/W
0
3
LWROD IRQPAS
R/W
2
0
R/W
1
0
(Initial value)
(Initial value)
RAME
R/W
0
1
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