DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 126
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 126 of 1246
- Download datasheet (7Mb)
4.5
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.4
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
4.6
Figure 4.4 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
Rev.4.00 Sep. 07, 2007 Page 94 of 1210
REJ09B0245-0400
Interrupt Control Mode
Trap Instruction
Stack Status after Exception Handling
SP
Figure 4.4 Stack Status after Exception Handling (Advanced Modes)
Status of CCR and EXR after Trap Instruction Exception Handling
0
2
Note: * Ignored on return.
(a) Interrupt control mode 0
(24 bits)
CCR
PC
1
1
I
CCR
SP
UI
—
—
(b) Interrupt control mode 2
I2 to I0
(24 bits)
Reserved*
EXR
CCR
PC
—
—
EXR
—
T
0
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