DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 276
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7.5.3
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one
byte or word is transferred in response to a single transfer request, and this is executed the number
of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.7 summarizes register functions in idle mode.
Table 7.7
Register
23
23
Legend:
MAR:
IOAR:
ETCR: Execute transfer count register
DTDIR: Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
Rev.4.00 Sep. 07, 2007 Page 244 of 1210
REJ09B0245-0400
H'FF
Memory address register
I/O address register
15
15
Idle Mode
MAR
Register Functions in Idle Mode
ETCR
IOAR
0
0
0
DTDIR = 0 DTDIR = 1 Initial Setting
Source
address
register
Destination
address
register
Transfer counter
Function
Destination
address
register
Source
address
register
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
Operation
Fixed
Fixed
transfer; transfer
ends when count
reaches H'0000
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