DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 164
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.1.3
Table 6.1 summarizes the pins of the bus controller.
Table 6.1
Rev.4.00 Sep. 07, 2007 Page 132 of 1210
REJ09B0245-0400
Name
Address strobe
Read
High write/write enable
Low write
Chip select 0
Chip select 1
Chip select 2/row
address strobe 2
Chip select 3/row
address strobe 3
Chip select 4/row
address strobe 4
Chip select 5/row
address strobe 5
Chip select 6
Chip select 7
Upper column address
strobe
Lower column address
strobe
Pin Configuration
Bus Controller Pins
Symbol
AS
RD
HWR
LWR
CS
CS
CS
CS
CS
CS
CS
CS
CAS
LCAS
0
1
2
3
4
5
6
7
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Strobe signal indicating that address output on
address bus is enabled.
Strobe signal indicating that external space is
being read.
Strobe signal indicating that external space is to
be written, and upper half (D
is enabled.
2-CAS DRAM write enable signal.
Strobe signal indicating that external space is to
be written, and lower half (D
is enabled.
Strobe signal indicating that area 0 is selected.
Strobe signal indicating that area 1 is selected.
Strobe signal indicating that area 2 is selected.
DRAM row address strobe signal when area 2 is
in DRAM space.
Strobe signal indicating that area 3 is selected.
DRAM row address strobe signal when area 3 is
in DRAM space.
Strobe signal indicating that area 4 is selected.
DRAM row address strobe signal when area 4 is
in DRAM space.
Strobe signal indicating that area 5 is selected.
DRAM row address strobe signal when area 5 is
in DRAM space.
Strobe signal indicating that area 6 is selected.
Strobe signal indicating that area 7 is selected.
2-CAS DRAM upper column address strobe
signal.
DRAM lower column address strobe signal.
Function
7
15
to D
to D
0
) of data bus
8
) of data bus
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