DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 467

• Manufacturer Part Number: DF2339VFC25V
• Description: IC H8S/2300 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2339VFC25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Port G Data Register (PGDR)
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG
PG
Bits 7 to 5 are reserved; they return an undefined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Port G Register (PORTG)
Note: * Determined by state of pins PG
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port G pins (PG
Bits 7 to 5 are reserved; they return an undefined value if read, and cannot be modified.
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTG contents are determined by the pin states, as
PGDDR and PGDR are initialized. PORTG retains its prior state in software standby mode.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
0
).
:
:
:
:
Undefined Undefined Undefined
Undefined Undefined Undefined
—
—
—
—
7
7
—
—
—
—
6
6
4
to PG
4
to PG
—
—
—
—
5
5
0
) must always be performed on PGDR.
0
.
PG4DR
R/W
PG4
— *
R
4
0
4
Rev.4.00 Sep. 07, 2007 Page 435 of 1210
PG3DR
PG3
R/W
— *
R
3
0
3
PG2DR
PG2
R/W
— *
R
2
0
2
PG1DR
REJ09B0245-0400
PG1
R/W
— *
R
1
0
1
4
PG0DR
to
PG0
R/W
— *
R
0
0
0