DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 129
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 129 of 1246
- Download datasheet (7Mb)
5.1
5.1.1
The chip controls interrupts by means of an interrupt controller. The interrupt controller has the
following features. This chapter assumes the maximum number of interrupt sources available in
these series—nine external interrupts and 52 internal interrupts.
• Two interrupt control modes
• Priorities settable with IPRs
• Independent vector addresses
• Nine external interrupt pins
• DTC and DMAC control
⎯ Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits
⎯ Interrupt priority registers (IPRs) are provided for setting interrupt priorities. Eight priority
⎯ NMI is assigned the highest priority level of 8, and can be accepted at all times
⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for
⎯ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
⎯ Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7
⎯ DTC and DMAC activation is controlled by means of interrupts
in the system control register (SYSCR)
levels can be set for each module for all interrupts except NMI
the source to be identified in the interrupt handling routine
edge can be selected for NMI
to IRQ0
Overview
Features
Section 5 Interrupt Controller
Rev.4.00 Sep. 07, 2007 Page 97 of 1210
REJ09B0245-0400
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