DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 879

• Manufacturer Part Number: DF2339VFC25V
• Description: IC H8S/2300 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2339VFC25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.1
The chip has an on-chip clock pulse generator (CPG) that generates the system clock (φ), the bus
master clock, and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-
speed clock divider, and a bus master clock selection circuit.
In the chip, the CPG has a medium-speed mode in which the bus master runs on a medium-speed
clock and the other supporting modules run on the high-speed clock, and a function that allows the
medium-speed mode to be disabled and the clock division ratio to be changed for the entire chip.
A clock from φ/2 to φ/32 can be selected.
20.1.1
Figure 20.1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Overview
Block Diagram
Oscillator
Figure 20.1 Block Diagram of Clock Pulse Generator
Section 20 Clock Pulse Generator
adjustment
circuit
Duty
System clock
to φ pin
speed clock
Medium-
divider
Rev.4.00 Sep. 07, 2007 Page 847 of 1210
φ/2 to φ/32
Internal clock
to supporting
modules
DIV
Bus master
selection
SCKCR
circuit
clock
REJ09B0245-0400
Bus master clock
to CPU, DTC,
and DMAC
SCK2 to SCK0