DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 336
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 336 of 1246
- Download datasheet (7Mb)
8.2.8
Note: * Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by
software.
Bit 7
SWDTE
0
1
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number for DTC software activation.
The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left-
shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
Rev.4.00 Sep. 07, 2007 Page 304 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
DTC Vector Register (DTVECR)
Description
DTC software activation is disabled
[Clearing conditions]
•
•
DTC software activation is enabled
[Holding conditions]
•
•
•
:
:
When the DISEL bit is 0 and the specified number of transfers have not ended
When 0 is written after a software activation data-transfer-complete interrupt is
issued to the CPU
When the DISEL bit is 1 and data transfer has ended
When the specified number of transfers have ended
During data transfer due to software activation
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
R/(W)
7
0
R/(W) *
6
0
R/(W) *
5
0
R/(W) *
4
0
R/(W) *
0
3
R/(W) *
2
0
R/(W) *
1
0
(Initial value)
R/(W) *
0
0
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