DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 410

• Manufacturer Part Number: DF2339VFC25V
• Description: IC H8S/2300 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2339VFC25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Port 7 Data Register (P7DR)
P7DR is a 6-bit readable/writable register that stores output data for the port 7 pins (P7
Bits 7 and 6 are reserved; they return an undefined value if read, and cannot be modified.
P7DR is initialized to H'00 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Port 7 Register (PORT7)
Note: * Determined by state of pins P7
PORT7 is a 6-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 7 pins (P7
Bits 7 and 6 are reserved, they return an undefined value if read, and cannot be modified.
If a port 7 read is performed while P7DDR bits are set to 1, the P7DR values are read. If a port 7
read is performed while P7DDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORT7 contents are determined by the pin states, as
P7DDR and P7DR are initialized. PORT7 retains its prior state in software standby mode.
Rev.4.00 Sep. 07, 2007 Page 378 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Bit
Initial value :
R/W
:
:
:
:
Undefined Undefined
Undefined Undefined
—
—
—
—
7
7
—
—
—
—
6
6
5
to P7
5
P75DR
to P7
R/W
P75
— *
0
) must always be performed on P7DR.
R
5
0
5
0
.
P74DR
R/W
P74
— *
R
4
0
4
P73DR
R/W
P73
— *
R
3
0
3
P72DR
R/W
P72
— *
R
2
0
2
P71DR
R/W
P71
— *
R
1
0
1
5
to P7
P70DR
R/W
P70
— *
R
0
0
0
0
).