DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 561
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 561 of 1246
- Download datasheet (7Mb)
11.1
The chip has a built-in programmable pulse generator (PPG) that provides pulse outputs by using
the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit
groups (group 3 to group 0) that can operate both simultaneously and independently.
11.1.1
PPG features are listed below.
• 16-bit output data
• Four output groups
• Selectable output trigger signals
• Non-overlap mode
• Can operate together with the data transfer controller (DTC) and DMA controller (DMAC)
• Inverted output can be set
• Module stop mode can be set
⎯ Maximum 16-bit data can be output, and output can be enabled on a bit-by-bit basis
⎯ Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit
⎯ Output trigger signals can be selected for each group from the compare match signals of
⎯ A non-overlap margin can be provided between pulse outputs
⎯ The compare match signals selected as output trigger signals can activate the DTC or
⎯ Inverted data can be output for each group
⎯ As the initial setting, PPG operation is halted. Register access is enabled by exiting module
outputs
four TPU channels
DMAC for sequential output of data without CPU intervention
stop mode
Section 11 Programmable Pulse Generator (PPG)
Overview
Features
Rev.4.00 Sep. 07, 2007 Page 529 of 1210
REJ09B0245-0400
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