DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 357
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 357 of 1246
- Download datasheet (7Mb)
Chain Transfer when Counter = 0: By executing a second data transfer, and performing re-
setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or
more repeat transfers.
An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed
to have been set to start at lower address H'0000. Figure 8.13 shows the memory map.
[1] For the first transfer, set the normal mode for input data. Set fixed transfer source address
[2] Prepare the upper 8-bit addresses of the start addresses for each of the 64k transfer start
[3] For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting
[4] Execute the first data transfer 64k times by means of interrupts. When the transfer counter for
[5] Next, execute the first data transfer the 64k times specified for the first data transfer by means
[6] Steps [4] and [5] are repeated endlessly. As repeat mode is specified for the second data
(G/A, etc.), CRA = H'0000 (64k times), and CHNE = 1, CHNS = 1, and DISEL = 0.
addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input
buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20.
the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the
first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above
input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the
transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer
destination address of the first data transfer and the transfer counter are H'0000.
of interrupts. When the transfer counter for the first data transfer reaches 0, the second data
transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to
H'20. The lower 16 bits of the transfer destination address of the first data transfer and the
transfer counter are H'0000.
transfer, an interrupt request is not sent to the CPU.
Rev.4.00 Sep. 07, 2007 Page 325 of 1210
REJ09B0245-0400
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