DF2339VFC25V Renesas Electronics America, DF2339VFC25V Datasheet - Page 272
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122258/df2339vfc25v_sml.jpg)
DF2339VFC25V
Manufacturer Part Number
DF2339VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2339VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 272 of 1246
- Download datasheet (7Mb)
Operation in each mode is summarized below.
Sequential Mode: In response to a single transfer request, the specified number of transfers are
carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC
when the specified number of transfers have been completed. One address is specified as 24 bits,
and the other as 16 bits. The transfer direction is programmable.
Idle Mode: In response to a single transfer request, the specified number of transfers are carried
out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the
specified number of transfers have been completed. One address is specified as 24 bits, and the
other as 16 bits. The transfer source address and transfer destination address are fixed. The transfer
direction is programmable.
Repeat Mode: In response to a single transfer request, the specified number of transfers are
carried out, one byte or one word at a time. When the specified number of transfers have been
completed, the addresses and transfer counter are restored to their original settings, and operation
is continued. No interrupt request is sent to the CPU or DTC. One address is specified as 24 bits,
and the other as 16 bits. The transfer direction is programmable.
Single Address Mode: In response to a single transfer request, the specified number of transfers
are carried out between external memory and an external device, one byte or one word at a time.
Unlike dual address mode, source and destination accesses are performed in parallel. Therefore,
either the source or the destination is an external device which can be accessed with a strobe alone,
using the DACK pin. One address is specified as 24 bits, and for the other, the pin is set
automatically. The transfer direction is programmable.
Sequential mode, idle mode, and repeat mode can also be specified for single address mode.
Normal Mode
• Auto-request
Rev.4.00 Sep. 07, 2007 Page 240 of 1210
REJ09B0245-0400
By means of register settings only, the DMAC is activated, and transfer continues until the
specified number of transfers have been completed. An interrupt request can be sent to the
CPU or DTC when transfer is completed. Both addresses are specified as 24 bits.
⎯ Cycle steal mode
⎯ Burst mode
The bus is released to another bus master after each byte or word transfer.
The bus is held and transfer continued until the specified number of transfers have been
completed.
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