HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 816

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 2.0, 08/02, page 776 of 788
Item
16.4.9 Operation Using
DTC
Table 16.7 Examples of
Operation Using DTC
16.6 Usage Notes
Table 16.11 I
Timing (with Maximum
Influence of tsr/tsf )
16.6.1 Module Stop Mode
Setting
Section 17 Keyboard
Buffer Controller
17.3 Register Descriptions
17.5 Usage Notes
17.5.2 Module Stop Mode
Setting
Section 18 Host Interface
X-Bus Interface (XBS)
18.1 Features
18.6 Usage Notes
18.6.2 Module Stop Mode
Setting
2
C Bus
Page
451
457
463
467
481
483
501
Revisions (See Manual for Details)
(Error)
Item
Transfer
request
processing
after last
frame
processing
(Error)
Item
t
Notes:
Added.
Description deleted.
The keyboard buffer controller has the following registers for
each channel. For details on the module stop control register,
refer to section 26.1.3, Module Stop Control Registers H and L
(MSTPCRH, MSTPCRL).
Added.
(Error)
(Correction)
Deleted.
Added.
SDASO
(slave)
Module stop mode setting
2.
3.
Master
Transmit Mode
1st time:
Clearing by
CPU
2nd time: End
condition
issuance by
CPU
t
1 t
cyc
Indication
SCLL
*
Value when the IICX bit is set to 1. When the IICX bit is cleared to
0, the value is (t
Calculated using the I
4700 ns min.; high-speed mode: 1300 ns min.).
3
–3 t
Slave
Transmit
Mode
Automatic
clearing on
detection of
end
condition
during
transmission
of dummy
data (H'FF)
cyc
*
2
(–t
Sr
)
SCLL
– 6t
Item
t
(Correction)
(Correction)
Item
Transfer
request
processing
after last frame
processing
SDASO
2
C bus specification values (standard mode:
cyc
(slave)
).
Master
Transmit
Mode
1st time:
Clearing by
CPU
2nd time:
Stop
condition
issuance by
CPU
t
1 t
cyc
SCLL
Indication
*
3
–12 t
Slave
Transmit
Mode
Automatic
clearing on
detection of
stop condition
during
transmission
of dummy
data (H'FF)
cyc
*
2
(–t
Sr
)