HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 476

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

13. Read the IRTR flag in ICSR.
14. If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state.
15. Clear the WAIT bit in CMR to cancel the wait mode.
16. Read the last ICDR receive data.
17. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL
Rev. 2.0, 08/02, page 436 of 788
User processing
(master output)
(master output)
(slave output)
If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop
condition.
Execute step [12] to read the IRIC flag to detect the end of reception.
Then, clear the IRIC flag. Clearing of the IRIC flag should be done while WAIT = 0. (If the
WAIT bit is cleared to 0 after clearing the IRIC flag and then an instruction to issue a stop
condition is executed, the stop condition may not be issued correctly.)
is high, and generates the stop condition.
SDA
SCL
SDA
Master tansmit mode
IRTR
ICDR
IRIC
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag is cleared.
At the rise of the 9th receive clock pulse for one frame
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
received. The master device outputs the receive clock continuously to receive the next data.
[1] TRS cleared to 0
Figure 16.16 Example of Master Receive Mode Operation Timing
9
A
IRIC cleard to 0
Master receive mode
[2] ICDR read
Bit 7
(dummy read)
1
Bit 6
(MLS = ACKB = 0, WAIT = 1)
2
Bit 5
3
Data 1
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
[6] IRIC clear
(to end wait insertion)
8
[4]IRTR=0
[3]
A
[4] IRTR=1
9
[3]
[5] ICDR read
Bit 7
Data 1
(Data 1)
1
Bit 6
2
Data 2
[6] IRIC clear
Bit 5
3
Bit 4
4
Bit 3
5