HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 151

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

5.8
5.8.1
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes
effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an
instruction such as BCLR or MOV, and if an interrupt is generated during execution of the
instruction, the interrupt concerned will still be enabled on completion of the instruction, so
interrupt exception handling for that interrupt will be executed on completion of the instruction.
However, if there is an interrupt request of higher priority than that interrupt, interrupt exception
handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be
ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.11
shows an example in which the CMIEA bit in the TMR's TCR register is cleared to 0.
The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the
interrupt is masked.
5.8.2
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
Internal
address bus
Internal
write signal
CMIEA
CMFA
CMIA
interrupt signal
Usage Notes
Conflict between Interrupt Generation and Disabling
Instructions that Disable Interrupts
ø
Figure 5.11 Conflict between Interrupt Generation and Disabling
TCR write cycle
TCR address
by CPU
Rev. 2.0, 08/02, page 111 of 788
CMIA exception handling