HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 347

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HD6432160

Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
13.3.4
SEDGR detects a rising edge on the timer connection input pins and the occurrence of 2fH
modification, and determines the phase of the IVI and IHI signals.
Bit
7
6
5
4
3
Edge Sense Register (SEDGR)
Bit Name
VEDG
HEDG
CEDG
HFEDG
VFEDG
Initial Value
0
0
0
0
0
R/W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
1
1
1
1
1
VSYNCI Edge
Detects a rising edge on the VSYNCI pin.
[Clearing condition]
When 0 is written in VEDG after reading VEDG = 1
[Setting condition]
When a rising edge is detected on the VSYNCI pin
HSYNCI Edge
Detects a rising edge on the HSYNCI pin.
[Clearing condition]
When 0 is written in HEDG after reading HEDG = 1
[Setting condition]
When a rising edge is detected on the HSYNCI pin
CSYNCI Edge
Detects a rising edge on the CSYNCI pin.
[Clearing condition]
When 0 is written in CEDG after reading CEDG = 1
[Setting condition]
When a rising edge is detected on the CSYNCI pin
HFBACKI Edge
Detects a rising edge on the HFBACKI pin.
[Clearing condition]
When 0 is written in HFEDG after reading HFEDG = 1
[Setting condition]
When a rising edge is detected on the HFBACKI pin
VFBACKI Edge
Detects a rising edge on the VFBACKI pin.
[Clearing condition]
When 0 is written in VFEDG after reading VFEDG = 1
[Setting condition]
When a rising edge is detected on the VFBACKI pin
Description
Rev. 2.0, 08/02, page 307 of 788

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