HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 433

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

The I
optional function.
This LSI has a two-channel I
subset of the Philips I
controls the I
16.1
IFIIC60A_000020020700
Although the product type name is identical, please contact Hitachi before using this optional
function on an F-ZTAT version product.
Selection of addressing format or non-addressing format
Conforms to Philips I
Two ways of setting slave address (I
Start and stop conditions generated automatically in master mode (I
Selection of the acknowledge output level in reception (I
Automatic loading of an acknowledge bit in transmission (I
Wait function in master mode (I
Wait function (I
Interrupt sources
2
C bus interface is provided as an optional function. Note the following point when using this
I
Clocked synchronous serial format: non-addressing format without an acknowledge bit, for
master operation only
Formatless (for IIC_0 only): non-addressing format with a clock pin dedicated for
formatless; for slave operation only
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement.
The wait can be cleared by clearing the interrupt flag.
A wait request can be generated by driving the SCL pin low after data transfer.
The wait request is cleared when the next transfer becomes possible.
Data transfer end (including when a transition to transmit mode with I
when ICDR data is transferred, or during a wait state)
Address match: When any slave address matches or the general call address is received in
slave receive mode with I
arbitration)
Start condition detection (in master mode)
Stop condition detection (in slave mode)
2
C bus format: addressing format with an acknowledge bit, for master/slave operation
Features
Section 16 I
2
C bus differs partly from the Philips configuration, however.
2
C bus format)
2
C bus (inter-IC bus) interface functions. The register configuration that
2
C bus interface (I
2
C bus interface. The I
2
C bus format (including address reception after loss of master
2
C Bus Interface (IIC) (Optional)
2
C bus format)
2
C bus format)
2
C bus format)
2
C bus interface conforms to and provides a
2
C bus format)
2
C bus format)
Rev. 2.0, 08/02, page 393 of 788
2
C bus format)
2
C bus format occurs,