HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 500

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

9. Note on when I
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
10. Note on IRIC flag clear when the wait function is used
Rev. 2.0, 08/02, page 460 of 788
In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a
large bus load capacity or where a slave device in which a wait can be inserted by driving the
SCL pin low is used, the stop condition instruction should be issued after reading SCL after the
rise of the 9th clock pulse and determining that it is low.
If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be
inserted by driving the SCL pin low is used when the wait function is used in I
master mode, the IRIC flag should be cleared after determining that the SCL is low, as
described below.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
ICXR.
SDA
IRIC
SDA
IRIC
SCL
SCL
Figure 16.33 IRIC Flag Clearing Timing When WAIT = 1
2
C bus interface stop condition instruction is issued
SCL = low detected
VIH
VIH
9th clock
Figure 16.32 Stop Condition Issuance Timing
SCL is detected as low
because the rise of the
waveform is delayed
[1] SCL = low determination
[1] SCL = low determination
Secures a high period
Secures a high period
[2] IRIC clear
[2] Stop condition instruction issuance
Stop condition generation
2
C bust interface