HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 640
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HD6432160
Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6432160.pdf
(829 pages)
- Current page: 640 of 829
- Download datasheet (5Mb)
23.8.2
When erasing flash memory, the erase/erase-verify flowchart shown in figure 23.12 should be
followed.
1. Prewriting (setting erase block data to all 0) is not necessary.
2. Erasing is performed in block units. Make only a single-block specification in erase block
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as
Rev. 2.0, 08/02, page 600 of 788
registers 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in
turn.
An overflow cycle of approximately (y + z +
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
before. The maximum number of repetitions of the erase/erase-verify sequence is N.
Erase/Erase-Verify
+
ms is allowed.
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