HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 502

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

12. Note on TRS bit setting in slave mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
13. Note on ICDR read in transmit mode and ICDR write in receive mode
Rev. 2.0, 08/02, page 462 of 788
In I
edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the
SCL pin (the time indicated as (a) in figure 16.35), the bit value becomes valid immediately
when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in
figure 16.35), the bit value is suspended and remains invalid until the rising edge of the 9th
clock pulse or the stop condition is detected. Therefore, when the address is received after the
restart condition is input without the stop condition, the effective TRS bit value remains 1
(transmit mode) internally and thus the acknowledge bit is not transmitted after the address has
been received at the 9th clock pulse.
To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in
figure 16.35. To release the SCL low level that is held by means of the wait function in slave
mode, clear the TRS bit to and then dummy-read ICDR.
If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0),
the SCL pin may not be held low in some cases after transmit/receive operation has been
completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before
ICDR is accessed correctly. To access ICDR correctly, read ICDR after setting receive mode
or write to ICDR after setting transmit mode.
SDA
TRS
SCL
2
C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising
ICXR.
transmission
Data
8
The rise of the 9th clock is detected
9
TRS bit setting
(a)
Figure 16.35 TRS Bit Set Timing in Slave Mode
ICDR dummy read
Restart condition
TRS bit setting is suspended in this period
1
Address reception
2
(b)
3
4
5
6
7
The rise of the 9th clock is detected
8
9
A