HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 649
HD6432160
Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6432160.pdf
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This LSI incorporates a clock pulse generator, which generates the system clock (ø), bus master
clock, and internal clock.
The clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit,
medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform
forming circuit. Figure 25.1 shows a block diagram of the clock pulse generator.
The bus master clock is selected as either high-speed mode or medium-speed mode by software
according to the settings of the SCK2 to SCK0 bits in the standby control register. For details on
the standby control register, refer to section 26.1.1, Standby Control Register (SBYCR).
The subclock input is controlled by software according to the EXCLE bit setting in the low power
control register. For details on the low power control register, refer to section 26.1.2, Low Power
Control Register (LPWRCR).
EXTAL
EXCL
XTAL
input circuit
Subclock
Oscillator
Figure 25.1 Block Diagram of Clock Pulse Generator
Section 25 Clock Pulse Generator
Waveform
correction
forming
circuit
circuit
Duty
count clock
øSUB
WDT_1
Clock select
circuit
System clock
to ø pin
speed clock
Medium-
divider
Internal clock
to peripheral
Rev. 2.0, 08/02, page 609 of 788
modules
ø/2
to f/32
ø
clock select
Bus master
circuit
Bus master clock
to CPU and DTC
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