HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 486

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HD6432160

Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
16.4.7
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred in synchronization with the internal
clock. Figures 16.26 to 16.28 show the IRIC set timing and SCL control.
Rev. 2.0, 08/02, page 446 of 788
(master output)
(master output)
(slave output)
User processing
Slave receive mode
STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to
0.
ICDRE
SDA
SDA
SCL
ICDR
IRIC
IRIC Setting Timing and SCL Control
R/
Figure 16.25 Example of Slave Transmit Mode Operation Timing
8
A
9
[2]
[3] IRIC clear
[3] ICDR write
Bit 7
[3] IRIC clear
1
Bit 6
2
(MLS = 0)
Bit 5
3
Bit 4
Data 1
4
Data 1
Bit 3
5
Slave transmit mode
Bit 2
6
Bit 1
7
Bit 0
8
[5] ICDR write
9
A
[4]
Data 2
Bit 7
[5] IRIC clear
1
Data 2
Bit 6
2

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