HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 815

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
Figure 16.13 Example of
Stop Condition Issuance
Operation Timing in
Master Receive Mode
(MLS = WAIT = 0, HNDS
= 1)
Figure 16.17 Example of
Stop Condition Issuance
Timing in Master Receive
Mode (MLS = ACKB = 0,
WAIT = 1)
16.6 Usage Notes
Page
432
437
454
(Error)
Revisions (See Manual for Details)
(Error)
(master output)
(Correction)
(master output)
1. Description amended.
(master output)
(master output)
(master output)
(master output)
(slave output)
(slave output)
(slave output)
User processing
User processing
User processing
ICDRR
ICDRF
SCL
SDA
ICDRF
ICDRR
SDA
IRTR
SCL
SDA
SCL
SDA
IRIC
SDA
IRTR
SDA
IRTR
ICDR
IRIC
IRIC
Data 2
Bit 1
Bit 1
Bit 0
Data 1
Data 1
Data 2
7
Data 2
[4] IRIC clear
7
[4] IRIC clear
8
Bit 0
[3]
[4] IRTR=0
Bit 0
Data 1
8
8
[6] IRIC clear
[6] Set ACKB = 1
[6] Set ACKB = 1
A
A
A
[3]
9
[3]
9
SCL is fixed low until ICDR is read
[4] IRTR=1
SCL is fixed low until ICDR is read
[7] Set ACKB=1
9
[8] Wait for one clock pulse
[3]
[7] ICDR read
Bit 7
[9] Set TRS=1
1
Bit 7
(Data 2)
Bit 7
1
1
[6] ICDR read (Data 2)
[7] ICDR read
Bit 6
2
Bit 6
Bit 6
(Data 2)
[11] IRIC clear
2
2
Bit 5
Data 2
Bit 5
Bit 5
3
Data 3
3
3
Data 2
Data 3
Data 2
Data 3
Bit 4
Bit 4
Bit 4
4
4
4
Rev. 2.0, 08/02, page 775 of 788
Bit 3
Bit 3
5
5
(master output)
(Correction)
(master output)
(slave output)
SCL is fixed low until ICDR is read
User processing
Bit 2
Bit 2
6
6
SCL
SDA
SDA
IRTR
ICDR
IRIC
SCL is fixed low until
stop condition is issued
Bit 1
Bit 1
Data 2
7
[9] IRIC clear
7
[9] IRIC clear
Bit 0
Bit 0
Bit 0
8
8
8
[11] Set BBSY=0 and
(Stop condition instruction issuance)
[11] Set BBSY=0 and
(Stop condition instruction issuance)
[3]
[4] IRTR=0
A
[8]
A
[8]
9
9
Data 1
SCP=0
SCP=0
[6] IRIC clear
A
Start condition generation
Stop condition generation
[4] IRTR=1
[7] Set ACKB=1
[10] ICDR read
9
[10] ICDR read
[8] Wait for one clock pulse
[3]
(Data 3)
(Data 3)
Bit 7
[9] Set TRS=1
1
Data 3
Data 3
[6] ICDR read (Data 2)
Bit 6
2
Data 2
Bit 5
[11] IRIC clear
3
Data 3
Bit 4
4