HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 302

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HD6432160

Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
11.7.2
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict.
11.7.3
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of
conflict.
If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs
in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of
the automatic addition is not written to OCRA. Figure 11.20 shows the timing for this type of
conflict.
Rev. 2.0, 08/02, page 262 of 788
Conflict between FRC Write and Increment
Conflict between OCR Write and Compare-Match
ø
Address
Internal write
signal
FRC input
clock
FRC
Figure 11.18 FRC Write-Increment Conflict
Write cycle of FRC
T 1
FRC address
T 2
N
Write data
M

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