HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 814
HD6432160
Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6432160.pdf
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Rev. 2.0, 08/02, page 774 of 788
Item
16.3.8 I
Control Register (ICXR)
Section 16 I
Interface (IIC) (Optional)
16.4.3 Master Transmit
Operation
Figure 16.9 Example of
Operation Timing in
Master Transmit Mode
(MLS = WAIT = 0)
16.4.4 Master Receive
Operation
2
C Bus Extended
2
C Bus
Page
422
429
430
Revisions (See Manual for Details)
[Clearing Conditions]
(Error)
ICDRF is set to 1 again.
(Correction)
ICDRE is set to 1 again.
(Error)
(Error)
The master device transmits data containing the slave
address and R/: (0: read) in the first frame following the start
condition issuance in master transmit mode, selects the slave
device, and then switches the mode for receive operation.
(Correction)
The master device transmits data containing the slave
address and R/: (1: read) in the first frame following the start
condition issuance in master transmit mode, selects the slave
device, and then switches the mode for receive operation.
Note: * Data write
User processing
timing in ICDR
ICDRS
Incorrect
operation
[4] BBSY set to 1
SCP cleared to 0
(start condition issuance)
Normal
operation
Address + R/
(Correction)
User processing
Note: Data write
ICDRS
in ICDR
prohibited
[4] BBSY set to 1
SCP cleared to 0
(start condition issuance)
Address + R/
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