HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 591

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

19.6
19.6.1
LPC operation can be enabled or disabled using the module stop control register. The initial
setting is for LPC operation to be halted. Register access is enabled by canceling module stop
mode. For details, refer to section 26, Power-Down Modes.
19.6.2
The host interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid
data contention. For example, if the host and slave processor both try to access IDR or ODR at the
same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be
used to allow access only to data for which writing has finished.
Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data
registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing
No
No
Usage Notes
Module Stop Mode Setting
Notes on Using Host Interface
Write 1 to IRQ1E1
ODR1 write
transferred?
OBF1 = 0?
All bytes
Figure 19.8 HIRQ Flowchart (Example of Channel 1)
Yes
Yes
Slave CPU
SERIRQ IRQ1 output
source clearance
SERIRQ IRQ1
Rev. 2.0, 08/02, page 551 of 788
Hardware operation
Software operation
Interrupt initiation
Master CPU
ODR1 read