HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 375

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

14.4.3
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/10, bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the 5(62 pin. The timing is shown in figure 14.5.
14.5
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is
generated by an overflow.
Table 14.2 WDT Interrupt Source
Name
WOVI
Overflow signal
(internal signal)
ø
OVF
Internal reset
signal
TCNT
5(62 Signal Output Timing
5(62
Interrupt Sources
5(62
5(62
signal
Interrupt Source
TCNT overflow
Figure 14.5 Output Timing of 5(62
H'FF
Interrupt Flag
OVF
5(62 signal
5(62
5(62
132 states
518 states
Rev. 2.0, 08/02, page 335 of 788
H'00
DTC Activation
Not possible