HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 38

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 16.10
Table 16.11
Section 17 Keyboard Buffer Controller
Table 17.1
Section 18 Host Interface X-Bus Interface (XBS)
Table 18.1
Table 18.2
Table 18.3
Table 18.4
Table 18.5
Table 18.6
Table 18.7
Table 18.8
Table 18.9
Section 19 Host Interface LPC Interface (LPC)
Table 19.1
Table 19.2
Table 19.3
Table 19.4
Table 19.5
Table 19.6
Table 19.7
Table 19.8
Section 20 D/A Converter
Table 20.1
Table 20.2
Section 21 A/D Converter
Table 21.1
Table 21.2
Table 21.3
Section 23 ROM
Table 23.1
Table 23.2
Table 23.3
Table 23.4
Table 23.5
Table 23.6
Section 25 Clock Pulse Generator
Table 25.1
Rev. 2.0, 08/02, page xxxvi of xxxviii
Permissible SCL Rise Time (t
I
Pin Configuration ..................................................................................................466
Pin Configuration ..................................................................................................48 5
Set/Clear Timing for STR Flags............................................................................493
Host Interface Channel Selection and Pin Operation ............................................494
Host Interface Operations from HIF Host, and Slave Operation...........................495
GA20 (P81) Set/Clear Timing...............................................................................496
Fast A20 Gate Output Signal.................................................................................497
Scope of HIF Pin Shutdown..................................................................................498
Input Buffer Full Interrupts ...................................................................................499
HIRQ Setting/Clearing Conditions .......................................................................500
Pin Configuration ..................................................................................................505
Register Selection..................................................................................................518
GA20 (P81) Set/Clear Timing...............................................................................539
Scope of Host Interface Pin Shutdown..................................................................543
Scope of Initialization in Each Host Interface Mode ............................................544
Receive Complete Interrupts and Error Interrupt ..................................................548
HIRQ Setting and Clearing Conditions.................................................................550
Pin Configuration ..................................................................................................554
D/A Channel Enable..............................................................................................555
Pin Configuration ..................................................................................................561
Analog Input Channels and Corresponding ADDR Registers...............................562
A/D Conversion Time (Single Mode) ...................................................................569
Differences between Boot Mode and User Program Mode...................................579
Pin Configuration ..................................................................................................585
Operating Modes and ROM ..................................................................................591
On-Board Programming Mode Settings................................................................591
Boot Mode Operation............................................................................................594
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate
is Possible..............................................................................................................595
Damping Resistance Values..................................................................................610
Fast A20 Gate Output Signals ..............................................................................541
2
C Bus Timing (with Maximum Influence of t
sr
) Values ................................................................455
Sr
/t
Sf
) .............................................457