HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 296

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input
capture signal is delayed by one system clock (ø). Figure 11.8 shows the timing for this case.
11.5.5
ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 11.9 shows how
input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and
IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0),
so that input capture is performed on both the rising and falling edges of FTIA.
Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however. In buffered input capture, if either set of two registers to which data
Rev. 2.0, 08/02, page 256 of 788
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read)
ø
FTIA
Input capture
signal
FRC
ICRA
ICRC
ø
Input capture
input pin
Input capture signal
Buffered Input Capture Input Timing
Figure 11.9 Buffered Input Capture Timing
M
m
n
M
n
n + 1
Read cycle of ICRA to ICRD
T 1
N
M
n
T 2
N
n
N + 1